Semiconductor memory device, power supply detector and semiconductor device

ABSTRACT

A semiconductor memory device comprises a n-channel type MOSFET in which a drain and a gate are connected to an external power supply and a source and a back gate are connected each other, a node connected to the source and the back gate of the n-channel type MOSFET, and a detector for detecting an input of the external power supply based on a potential of the node

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of the priorityfrom the prior Japanese Patent Application No. 2006-023258 filed on Jan.31, 2006: the entire contents of which are Incorporated herein byreference

BACKGROUND

1. Field of the of the Invention

This invention relates to a semiconductor memory device, a power supplydetector and a semiconductor device each having a circuit for detectingan applying of an external power supply.

2. Description of Related Art

Recently, accompanying with the spread of a mobile instrument such as aportable telephone, it has been required to provide a low power, a lowvoltage operation and a proof at a wide temperature range. In suchcircumstances, various problems which have not been consideredconventionally have been appeared. As one of the problems, there is anoperation margin of a power supply input detection circuit (power-oncircuit). The power input detecting circuit is one for outputting atrigger signal to apply a voltage used in a semiconductor memory deviceby detecting that a power from the outside is supplied.

In the semiconductor memory device using in the mobile equipment and thelike, MOSFET (Metal-oxide-Semiconductor Field Effect Transistor) whichhas a relatively high threshold (Vth) is adopted due to low power,wherein it is required to have a margin for the low voltage operationand a guarantee at a wide temperature range (for example, −40 to 100degree Celsius). Accordingly, it is required to have enough margins inthe power supply input detection circuit of the power system.

In connection with these request, in a typical power supply inputdetection circuit using a diode-connected p-channel type MOSFET theeffect by the temperature property of a threshold of the p-channel typeMOSFET is large. Therefore, it is difficult to secure enough margin withrespect to both a minimum power voltage value which can correctly latcha fuse data (fuse-latch limit voltage) and minimum power voltage valuethat the semiconductor memory device can operate. That is, in a typicalpower supply input detection circuit, as the requirements to the lowerpower, low voltage operation and wide temperature range guarantee becomesevere, since an operation margin becomes insufficient, it is expectedthat the semiconductor memory device could not exhibit enoughperformance.

As a known technique relating to the power supply input detectioncircuit, the use of a diode-connected n-channel MOS transistor having agate and a drain connected (for example, Japanese Patent Laid-openApplication Hei 9-181586, FIG. 2 and the paragraph 0018). However, asdescribed in the above reference, when the structure in which the gateand the drain of the n-channel MOS transistor are connected is adopted,it is difficult to suitably perform the detection of power-on at a lowpower voltage and low temperature, because a threshold increases due tothe back-bias effect.

SUMMARY

In view of the above circumstances an object of the invention is toprovide a semiconductor memory device, a power supply detector and asemiconductor device which can reduce the variation because of thetemperature in possible voltage range of the output of the power inputdetection circuit and secure enough margin in both a minimum powervoltage which can exactly latch a fuse data and a minimum power voltagewhich can act in the semiconductor memory device.

To solve the above problems, a semiconductor memory device, a powersupply detector and a semiconductor device comprise an n-channel typeMOSFET in which a drain and a gate thereof are connected to an externalpower supply, a node connected to a source and a back gate of then-channel type MOSFET and a detector for detecting an applying of theexternal power supply based on a potential of the node.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing showing a structure of a power supply inputdetection circuit of a semiconductor memory device according to a firstembodiment of the present invention.

FIG. 2 is a block diagram for explaining a power-on sequence of thesemiconductor memory device using the power supply input detectioncircuit shown in FIG. 1.

FIG. 3 is a drawing showing a temperature dependency of a node A of thepower supply input detection circuit shown in FIG. 1.

FIG. 4 is a drawing showing a temperature dependency of an output of thepower supply input detection circuit shown in FIG. 1.

FIG. 5 is a drawing showing a comparison of the temperature dependencyof output between the power supply input detection circuit shown in FIG.1 and a power supply input detection circuit shown in FIG. 9.

FIG. 6 is a drawing showing a setting range of output of the powersupply input detection circuit shown in FIG. 1

FIG. 7 is a block diagram for explaining the power-on sequence using apower supply input detection circuit according to a second embodiment.

FIG. 8 is a drawing showing a structure of the power supply inputdetection circuit shown in FIG. 7.

FIG. 9 is a drawing showing a structure of conventional and typicalpower supply input detection circuit in comparison with the presentinvention.

FIG. 10 is a drawing showing a temperature dependency of a node A in thetypical power supply input detection circuit shown in FIG. 9.

FIG. 11 is a drawing showing a temperature dependency of output of thetypical power supply input detection circuit shown in FIG. 9.

FIG. 12 is a drawing showing a structure of option fuse latch circuitshown in FIG. 2.

FIG. 13 is a drawing showing a setting range of output in the typicalpower supply input detection circuit shown in FIG. 9.

DETAILED DESCRIPTION

The embodiments of the present invention will be described below. FIG. 1is a drawing showing a structure of a power supply input detectioncircuit of the semiconductor memory device according to a firstembodiment of the present invention. The power supply input detectioncircuit is constituted of an n-channel type MOSFET 1, a p-channel typeMOSFET 2, an n-channel type MOSFET 3, a resistance R1, and threeinverters 4, 5 and 6. A drain of the n-channel type MOSFET 1 isconnected to an input terminal 15 of an external power supply (VEXT). Agate of the n-channel type MOSFET 1 is connected to self-drain. That is,the drain and the gate of the n-channel type MOSFET 1 are connected witheach other. A source (a node A) and a back gate of the n-channel typeMOSFET 1 are connected each other and the node A is grounded through theresistance R1. Further, the source of the n-channel type MOSFET 1 isconnected to respective gates of the p-channel type MOSFET 2 and then-channel type MOSFET 3 which are complementarily connected The outputs(drains) of the complementarily connected the p-channel type MOSFET 2and the n-channel type MOSFET 3 are connected to a first input terminalof a first inverter 4 among three inverters 4, 5, 6.

In this power supply input detection circuit, a potential of the node Ais in a level of VEXT-Vthn1 (Vthn1: threshold of the n-channel typeMOSFET), and increases as a voltage of the external power supply (VEXT)increases. This increase of the potential of the node A is monitored inthe p-channel type MOSFET 2 and the n-channel type MOSFET 3. When thepotential of the node A become higher than the circuit threshold (inbrief, the threshold of the n-channel type MOSFET 3) of the circuitconstituted of these two MOSFETs, the n-channel type MOSFET 3 dischargesa node B and makes to a potential of the ground power source (VSS; logic“L”) Then the inverter 4 charges a node C to be a potential of theexternal power supply (VEXT; logic “H”) and the next inverter 5discharges a node D to be a potential of the ground power source (VSS;logic “L”). Further, the next inverter 6 charges an INITE node, whichoutputs an INITE signal that is a detection signal of the external powersupply input, to be a potential of the external power supply (VEXT;logic “H”). By outputting this INITE signal, the above power-on sequenceis started.

FIG. 2 is a block diagram for explaining the power-on sequence of thesemiconductor memory device with the output of the power supply inputdetection circuit shown in FIG. 1 as a trigger

When the external power supply (VEXT) is applied, the power supply inputdetection circuit 21 detects that the external power supply is appliedbased on a threshold, and outputs the INITE signal (logic “H”). By thisINITE signal, the applying of the external power supply is detectedwithin the semiconductor memory device, and the power-on operation ofthe internal power supply circuit is started.

A VINT monitor circuit 22 receives the INITE signal, and monitors thestart of applying a reference potential which forms a base of theinternal power supply (VINT) of the semiconductor memory device and allinternal potential The VINT monitor circuit 22 detects that levels ofthe internal power supply (VINT) and reference potential are arrived torespective setting levels, then outputs the detection signals to anoption fuse-latch circuit 23 and a delay circuit 24.

When the option fuse-latch circuit 23 receives the detection signal, forexample, the option fuse-latch circuit 23 latches fuse data for trimminga DC level and the like. As above, in the option fuse-latch circuit 23,by obtaining the fuse data of DC system such as the DC level in an earlystep and determining them, it is possible to suppress the change ofpotential after the completion of the power-on operation. Further, thedata that the option fuse-latch circuit 23 latches is not limited to theDC system fuse data and the other data may be allowable.

On the other hand, the delay circuit 24 delays for a predetermined timeand outputs the output of the VINT monitor circuit 22 to a step-up powersupply circuit 25 (boost converter) as a trigger signal. The step-uppower supply circuit 25 receives the trigger signal and startsgenerating a drive system potential (Vpp) of a word line. When thedriving system potential (Vpp) of the word line reaches to apredetermined level, next a step-down power supply circuit 26 starts agenerating-operation of a cell substrate system potential (Vbb) When thepower supply voltage of the cell substrate system reaches to the settinglevel, an R/D fuse-latch circuit 27 latches redundant fuse data, andinitializes an internal node based on the latched data. Thereby, thepower-on operation of the semiconductor memory device is completed.

Here, the drive system potential Vpp of the word line and the potentialVbb of the cell substrate are described for simplifying the explanationof the power-on sequence. The explanation of the other internalpotential is omitted

As the semiconductor memory device used in the mobile instrument, aMOSFET having relatively high threshold (Vth) due to a lower power isemployed. Further, it is required to have a margin of the lowest voltage(Vccmin) which guarantees an operation of the semiconductor memorydevice and a wide range of guarantee temperature (for example, −40 to100 degree Celsius guarantee temperature). Accompanying with theserequirements, it becomes necessary to have an enough margin in the powersupply input detection circuit of the power supply system. Next, we willdescribe the reason thereof.

(The typical power supply input detection circuit.) FIG. 9 shows astructure of a typical power supply input detection circuit fordetecting an external power supply input to a semiconductor memorydevice. In the typical power supply input detection circuit, adiode-connected p-channel type MOSFET 31 is used. That is, in thetypical power supply input detection circuit, by the diode-connectedp-channel type MOSFET 31, a threshold of p-channel type MOSFET ismonitored, and by a next step n-channel type MOSFET 33 a threshold ofn-channel type MOSFET is monitored. When a voltage of the external powersupply (VEXT) is higher than the sum (Vthn+Vthp) of the threshold of then-channel type MOSFET and the threshold of the p-channel type MOSFET, anINITE signal is outputted from the power supply input detection circuit.Further, in the other word, in this typical power supply input detectioncircuit, a power-on sequence is started by detecting that an externalpower supply voltage rises up to a level of which the external powersupply voltage can operate all elements within the semiconductor memorydevice.

This typical power supply input detection circuit has no problem whenused in a semiconductor memory device of which the external power supplyvoltage is relatively high and the temperature guarantee range is not sowide. However, in order to guarantee an operation at a low power, aMOSFET having a high threshold is used, and when a low voltage operationand/or wide temperature guarantee range are required, many problemsoccur.

In the typical power supply input detection circuit shown in FIG. 9, thetemperature property in the case that an external power supply (VEXT) isapplied, a potential of a node A becomes VEXT-Vthp (Vthp: a threshold ofp-channel type MOSFET 31) and rises up, is shown in FIG. 10. Since thethreshold of MOSFET has a minus temperature dependency in both then-channel type MOSFET and the p-channel type MOSFET, the temperaturedependency thereof is high as a low temperature and is low at a hightemperature Therefore the rise of the potential of the node A is fastwhen high temperature. Since the later circuits are operated based onthe node A having a temperature dependency, later circuits have similartemperature dependency. That is, as shown in FIG. 11 at a hightemperatures the power supply input detection circuit operates andoutputs the INITE signal during a low voltage of the external powersupply (VEXT).

Such dispersion of output potential of the INITE signal brings seriousproblems because as the minimum voltage value (Vccmin) which guaranteesthe operation of the semiconductor memory device becomes lower, apermissible margin of the dispersion of output potential is lost.Further, the effect to the latch action of the fuse data by the optionfuse-latch circuit 23 becomes serious problems.

FIG. 12 is a drawing showing a structure of the option fuse-latchcircuit 23 shown in FIG. 2. At an initial states both a control signal 1(VINT system signal) and a control signal 2 (VINT system signal) have alogic level “L” (VSS). A node F is pre-charged to a VINT level with ap-channel type MOSFET 47 and p-channel type MOSFET 49 When a logic levelof the control signal 1 is “H” (VINT), the p-channel type MOSFET 47turns to cut-off. Next, the logic level of the control signal 2 turns to“H”, thereby n-channel type MOSFET 48 turns to on. Here, if a fuseelement Fu is cut, since a path which discharge a charge of the node Fto a ground power supply (VSS) through a n-channel type MOSFET 48 doesnot exist, the node F holds a logic level “H”. If the fuse element isnot cut, since the charge of the node F is discharged to a ground powersupply (VSS) through the n-channel type MOSFET 48, a logic level of thenode F turns to “L”, thereby the fuse data being latched.

That is, in this option fuse-latch circuit 23, an action which latchesfuse data becomes a ratio action in which the latch data are determineddepending on the action which has stronger behavior between adischarging action of n-channel type MOSFET 48 and a charging action ofp-channel type MOSFET 49. Owing to this, when a level of the controlsignal 2, an internal power supply (VINT) or the like is low, even if afuse element is not cut, since a charge of the node F does not enoughdischarge into a ground power supply (VSS) through the n-channel typeMOSFET 48 (the charge with a p-channel type MOSFET 49 is superior) thelogic level of the node F remains “H”. Consequently, it happens that thecorrect latch of fuse data is impossible.

For normally latching fuse data, it is required that a size ratio of n/pchannel type MOSFETs, a level of the internal power supply (VINT), andthe like are in optimum conditions. Further, to make larger the marginof the semiconductor memory device at low voltage operation, it isnecessary to make power-on a power supply system with a voltage lowerthan the minimum voltage guaranteed in operation. These relations areshown in FIG. 13. In the temperature property 1 of the INITE signalshown in FIG. 13, the possible range of the INITE signal is shifted to ahigh voltage side so as to have enough margins to the minimum powersupply voltage value (fuse-latch limit voltage) which can correctlylatch fuse data. However, in this the margin of low voltage operation isinsufficient. And in the temperature property 2 of the INITE signal, therange of the INITE signal is shifted to a low voltage side to improvethe margin at low voltage operation. In this case, the margin isinsufficient to the fuse-latch limit voltage. Accordingly, consideringthe fluctuation of PST dispersion of INITE signal, ideally, it isdesirable to have margins to both the fuse-latch limit voltage and thelow voltage operation as the temperature property 3 of the INITE signal.However, in the typical power supply input detection circuit using adiode-connected of p-channel type MOSFET, the effect by the temperaturedependency of threshold of the p-channel type MOSFET is large, thus itis difficult to have enough margin to both fuse-latch limit voltage andlow voltage operation. That is, in the typical power supply inputdetection circuit, as the requirements for the low powers the lowvoltage operation and the wide temperature range guarantee becomessevere, an operation margin becomes insufficient, hence it is expectedto be difficult to exhibit enough performance as a semiconductor memorydevice.

(A Power Supply Input Detection Circuit of the Present Invention)

Main differences between a power supply input detection circuit of thepresent invention shown in FIG. 1 and a typical power supply inputdetection circuit shown in FIG. 9 are as follows. In the presentinvention, instead of a diode-connected p-channel type MOSFET 31, ann-channel type MOSFET 1 in which a drain is connected with a gate and asource is connected with a back gate is used. Generally, the temperaturedependency of threshold of the n-channel type MOSFET is smaller thanthat of the p-channel type MOSFET. Therefore, as shown in FIG. 3, thetemperature dependency of the potential of the node A which rises at thelevel of the VEXT-Vthn1 (Vthn1: the threshold of the n-channel typeMOSFET 1) is decreased. As a result, as shown in FIG. 4, the temperaturedependency of the INITE signal which is outputted from the power supplyinput detection circuit is decreased.

Thus, by using the n-channel type MOSFET 1 in which a drain is connectedwith a gate and a source is connected with a back gate, as shown in FIG.5, it is possible to suppress the rate of fluctuation of level of theINITE signal in the power supply input detection circuit as to thetemperature, compared with a power supply input detection circuit usinga diode-connected p-channel type MOSFET. Therefore, it becomes easily toset a power-on voltage (voltage at the time that the INITE signal isoutputted from the power supply input detection circuit). That is, asshown in FIG. 6, it is possible to take a large margin for thefuse-latch limit voltage and for the low voltage operation of thesemiconductor memory device, because the fluctuation of the INITE signalbased on the PVT dispersion can be suppressed.

Further, as the known power supply input detection circuit disclosed inJapanese Patent Laid-open Application No. Hei 9-181586, simpleconnecting the drain and the gate of the n-channel type MOSFET isdifficult to suitably make a power-on detection at the time of low powersupply voltage/low temperatures due to the influence of the effect ofback bias. In contrast, in the embodiment of the present invention, byconnecting the source and the back gate each other, the above problem iscancelled, because the threshold of n-channel MOSFET itself can beaccurately monitored.

Next, we will describe a second embodiment of the present invention. Thefeature of the second embodiment is that as shown in FIG. 7, in order toexactly latch a fuse information, a quasi-fuse-latch circuit which is anexternal voltage threshold detector for monitoring that the externalpower supply voltage rises to a voltage capable of latching the fuseinformation, is incorporated into a power supply input detection circuit21 a. Here, the power supply input detection circuit 21 a is allowed touse both the n-channel type MOSFET in which the drain is connected withthe gate and the source is connected with the back gate, and thediode-connected p-channel type MOSFET.

FIG. 8 is a drawing showing a structure of the power supply inputdetection circuit 21 a using the n-channel type MOSFET 1 in which thedrain is connected with the gate and the source is connected with theback gate and a quasi-fuse-latch circuit 28. As shown in this FIG. 8,the quasi-fuse-latch circuit 28 has substantially an equal circuitconstant with a typical option fuse-latch circuit 23 shown in FIG. 12.That is, the quasi-fuse-latch circuit 28 has a p-channel type MOSFET 7and an n-channel type MOSFET 10 for pre-charging which receives anoutput of the inverter 4 (the node C) at a gate, and an n-channel typeMOSFET 8 for a fuse set which receive an output of the inverter 6 (thenode E) at a gate.

Respective sources of the p-channel type MOSFET 7 and the n-cannel typeMOSFET 10 for pre-charging are connected to an internal power supply(VINT). The drain of the p-channel type MOSFET 7 and the drain of then-channel type MOSFET 8 are connected to the latch node F. The latchnode F is connected to an input terminal of an inverter 12. An outputterminal of the inverter 12 is connected to respective gates of thep-channel type MOSFET 9 and the n-channel type MOSFET 11. And the outputterminal of the inverter 12 is connected to an input terminal of aninverter 13. An output terminal of the inverter 13 is connected to aninput terminal of a level shifter 15 which is a conversion circuit fromthe VINT power supply to the VEXT power supply. An output terminal ofthe level shifter 15 is connected to an input terminal of an inverter14, and the INITE signal is outputted from the output terminal of theinverter 14.

Since such quasi-fuse-latch circuit 28 is incorporated into the powersupply input detection circuit 21 a, it is possible to minimize (minimumvalue which can fuse-latch) the power-on voltage of the semiconductormemory device.

Next, we will describe an operation of the power supply input detectioncircuit 21 a using the n-channel type MOSFET 1 in which the drain isconnected with the gate and the source is connected with the back gateand the quasi-fuse-latch circuit 28 which is the external voltagethreshold detector.

A level of the node A is VEXT-Vthn1 (Vthn1: the threshold of then-channel type MOSFET 1), and the level rises with the increase ofvoltage of the external power supply (VEXT). In this embodiment, then-channel type MOSFET 1 in which the drain is connected with the gateand the source is connected with the back gate is used. Accordingly, theratio of variation to the temperature of the node A is about ½ to ⅓compared with that of a diode-connected p-channel type MOSFET.

The level rising of the node A is monitored at the p-channel type MOSFET2 and the n-channel type MOSFET 3. If the level of the node A rises morethan the circuit threshold of circuit (in brief, the threshold ofn-channel type MOSFET 3) constituted of these two MOSFETs, the p-channeltype MOSFET 2 cuts off and the n-channel type MOSFET 3 discharges thenode B, so as to reduce the level to the level of the ground powersupply (VSS; logic “L”). Then the inverter 4 charges the node C andmakes the level to the level of the external power supply (VEXT; logic“H”), and the next step inverter 5 discharges the node D so as to reducethe level to the level of the ground power supply (VSS; logic “L”).Further the next step inverter 6 charges the node E to be the level ofthe external power supply (VEXT; logic “H”).

At an initial state, since the logic levels of the node C and the node Fare both the logic “L”, the latch node F is pre-charged to a potentialof the internal power supply (VINT) by the p-channel type MOSFET 7 andthe p-channel type MOSFET 9. When the logic level of the node C becomes“H”, the p-channel type MOSFET 7 becomes cut-off. Subsequently, thelogic level of the node F becomes “H”, thereby a n-channel type MOSFET 8becomes on. Then, the discharge of the latch node F by the n-channeltype MOSFET 8 and the charge of the latch node F (fuse-latch operation)by the p-channel type MOSFET 9 are simultaneously performed. At thistime, the potential of the latch node F rises. If the capacity ofdischarge of the n-channel type MOSFET 8 exceeds the capacity of chargeof the p-channel type MOSFET 9, the latch is reversed, and the latchnode F is discharged to the logic level “L” of the ground power supply(VSS). As the result, an INITE signal is outputted from the power supplydetection circuit 21 a through the inverters 12, 13, and 14.

Here, the quasi-fuse-latch circuit 28 has substantially an equal circuitconstant as an actual fuse latch circuit for example, option fuse-latchcircuit 23, R/D fuse-latch circuit 27 and the like) within thesemiconductor memory device. Therefore, in the quasi-fuse-latch circuit28, when the latch of fuse data is normally conducted, the power-onsequence proceeds and it is guaranteed that actual fuse data (forexample, product fuse information, redundancy information) within thesemiconductor memory device can be exactly read.

Further, the circuit constant of the quasi-fuse-latch circuit 28 may beset to the severe value than that of the actual fuse-latch circuit tosecure a value larger than the margin of the minimum power supplyvoltage value.

As mentioned above, by incorporating the quasi-fuse-latch circuit 28into the power supply input detection circuit 21 a, even if the outputrange of the INITE signal is extended in order to obtain a low voltageoperation margin of the semiconductor memory device, unless the sequenceof the quasi-fuse-latch circuit 28 proceed, the power-on sequence of thepower system does not proceed. So that the latch error of the fuseinformation in the later fuse latch circuit (for example, optionfuse-latch circuit 23, R/D fuse-latch circuit 27, and the like) can besuppressed.

Here, the quasi-fuse-latch circuit 28 which is an external voltagethreshold detector is not limited to an imitated fuse-latch circuit, butthe other imitated circuit for determining a power on voltage may beallowable.

As described above, according to the embodiments of the presentinvention, by using the n-channel type MOSFET 1 in which the drain isconnected with the gate and the source is connected with the back gate,it becomes possible to decrease the temperature dependency of the INITEsignal, and by using the quasi-fuse-latch circuit 28, it becomespossible to obtain the maximum margin as a margin of minimum voltagevalue which guarantees the operation of the semiconductor memory device.Therefore, the operation margin for the low power/low voltageoperation/guarantee at wide temperature can be secured.

According to the semiconductor memory device of the present invention,by decreasing the fluctuation depending on the temperature in the rangeof voltage in which the power supply input detection circuit can beemployed, it is possible to secure enough margin to both the minimumpower supply voltage that can exactly latch fuse data and the minimumpower supply voltage that can operate the semiconductor memory device.

Further, the semiconductor memory device of the present invention is notlimited to the above embodiments but includes any modifications whichcome within the scope which does not depart from that of gist of theinvention.

1. A semiconductor memory device, comprising: an n-channel type MOSFETin which a drain and a gate thereof are connected to an external powersupply, and a source and a back gate thereof are connected each other; anode which is connected to the source and the back gate of the n-channeltype MOSFET; and a detector for detecting an applying of the externalpower supply based on a potential of the node.
 2. The semiconductormemory device according to claim 1, wherein the detector comprises ann-channel type MOSFET and a p-channel type MOSFET which are connectedcomplementarily each other
 3. The semiconductor memory device accordingto claim 1, further comprising an external voltage detector whichoutputs a power supply detection signal by detecting that a voltage ofthe external power supply reaches to a predetermined value by receivingan output of the detector.
 4. The semiconductor memory device accordingto claim 3, further comprising: an internal power generator whichoutputs an internal power supply based on the power supply detectionsignal; and a fuse-latch circuit which latches fuse data using theinternal power supply.
 5. The semiconductor memory device according toclaim 4, wherein the predetermined value of the external voltagedetector is a voltage value of which the fuse-latch circuit can latchthe fuse data in the fuse-latch circuit.
 6. The semiconductor memorydevice according to claim 3, wherein the external voltage detectorcomprises a quasi-fuse-latch circuit having a circuit constant which issubstantially an equal circuit constant to that of the fuse-latchcircuit.
 7. The semiconductor memory device according to claim 1,further comprising an inverter which reverses an output of the detector.8. A power supply detector, comprising: a first n-channel type MOSFET inwhich a drain and a gate thereof are connected to a power supply, and asource and a back gate thereof are connected each other; and a secondn-channel type MOSFET and a first p-channel type MOSFET which areconnected complementarily each other, each of the second n-channel typeMOSFET and the first p-channel type MOSFET having a gate connected tothe source and the back gate of the first n-channel type MOSFET and adrain outputting a detection output which detects an applying of thepower supply.
 9. The power supply detector according to claim 8, furthercomprising an inverter which reverses the detection output.
 10. Thepower supply detector according to claim 9, wherein the invertercomprises a plurality of inverters of which uneven numbers of invertersare series connected.
 11. A semiconductor device which has a powerdetector, comprising: a first n-channel type MOSFET in which a drain anda gate thereof are connected to an external power supply, and a sourceand a back gate thereof are connected each other; and a second n-channeltype MOSFET and a first p-channel type MOSFET which are connectedcomplementarily each other, each of the second n-channel type MOSFET andthe first p-channel type MOSFET having a gate connected to the sourceand the back gate of the first n-channel type MOSFET and a drainoutputting a detection output which detects an applying of the externalpower supply.
 12. The semiconductor device according to claim 11,further comprising an external voltage detector for outputting a powersupply detection signal by detecting that a voltage of the externalpower supply reaches to a predetermined value by receiving an output ofthe power supply detector.
 13. The semiconductor device according toclaim 12, further comprising: an internal power generator for outputtingan internal power supply to be used within the semiconductor device; anda fuse-latch circuit for latching fuse data by use of the internal powersupply.
 14. The semiconductor device according to claim 12, wherein thepredetermined value of the external voltage detector is a voltage ofwhich the fuse-latch circuit can latch the fuse-latch data.
 15. Thesemiconductor device according to claim 12, wherein the external voltagedetector comprises a quasi-fuse-latch circuit having a circuit constantwhich is substantially an equal circuit constant to that of thefuse-latch circuit.
 16. The semiconductor device according to claim 11,further comprising an inverter which reverses an output of the powerdetector.
 17. The semiconductor device according to claim 16, whereinthe inverter comprises a plurality of inverters of which uneven numbersof inverters are series connected.
 18. The semiconductor deviceaccording to claim 16, wherein the inverter comprises: a first inverter,in which an input thereof and respective drains of the second n-channeltype MOSFET and the first p-channel type MOSFT connected complementarilyare connected; a second inverter in which an input thereof and an outputof the first inverter are connected; and a third converter in which aninput thereof and an output of the second inverter are connected. 19.The semiconductor device according to claim 18, further comprising: athird n-channel type MOSFET and a second p-channel type MOSFET which arecomplementarily connected, wherein the output of the first inverter isconnected to a gate of the second p-channel type MOSFET, an output ofthe third inverter is connected to a gate of the third n-channel typeMOSFET, and respective drains of the third n-channel type MOSFET and thesecond p-channel type MOSFET output a quasi-fuse data.